This section should be easy. There are only 4 components on it. 2 surface mount IC's and 2 chip caps. Well, there is only 1 shown on the schematic here but C70 is right in the area of U6 so we'll do it also. Lets get started.
Looks easy enough. I don't think we need the parts table for 4 parts so lets dig out the parts. C70 is the same as C69, a 0.1ufd cap. If you have a anti-static wrist strap, put it on while handling the IC's. Also an anti-static mat would be good. Once the components are soldered onto the board they are reasonably safe.
Locate the 2 IC's. They will look like this. Pin 1 locators are done different ways. Generally, if the writing is right side up, pin 1 will be in the lower left corner. Otherwise look for a band, a dot, or a bevel.
Here's where the parts go. Now you can see why we are installing C70. It's doing some bypassing on the power pin of U6.
The new solder joints are de-fluxed and inspected for bridges. The bottom should now look like this. Time to test!
Testing the divider
Apply power and check the current. Mine drew 16.6ma.
Install JP1 in the left hand position which is the divide by 4 position. If you decide turn the board over and probe directly on the IC's, be extremely careful as if you slip, you may short something out. The safest way is to use the drawing above. If the waveforms are there, you don't need to check anything else.
Probe either the QSE CLK 1 or QSE CLK 2 point. You should have a square wave around 5 volts in amplitude. You may see more or less ringing depending on where you hook your probe ground. Use the probe mounted ground clip. We have about 2.8 divisions X 50ns=140ns 1/140ns=7.143 Mhz. That's close enough to tell us that it's working. Check the other CLK test point. It should look the same.
Here's why you don't transmit a square wave. The big spike is 0 Mhz. The second from the left is our 7 Mhz clock signal. The rest are the odd harmonics of the 7 Mhz.
Install JP1 in the right hand position. This is the divide by 8 setting. Once again check the 2 CLK test points. Here we have about 5.6 divisions x 50ns for a period of 280ns. 1/280ns =3.571 Mhz.
Lots more harmonics here!
Now the most important waveform is the I/Q signal phase comparison between CLK 1 and CLK 2. It needs to be at a 90 degree phase shift. If you have trouble seeing the phase shift, remember to trigger on the "I" channel only.
With the divider done, the next stage we will build and test is the op-amps and input transformer. This will allow us to test them independent of all the circuitry that we have completed.